1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device referred to as a system LSI a memory and a logic integrated on a common semiconductor substrate (chip). More specifically, the present invention relates to a configuration for externally testing an embedded memory allowing the number of input/output data bits to be varied with metal slicing.
2. Description of the Background Art
A DRAM-embedded system LSI having a DRAM (dynamic random access memory) and a logic device or a microprocessor integrated on a common semiconductor substrate (chip) has widely been used in recent years. Compared to a conventional system having a discrete DRAM and a logic device or a microprocessor mounted on a printed board with soldering or the like, such DRAM-embedded system LSI has following advantages.
(1) There is no restriction by a pin terminal. Therefore, width of a data bus between the DRAM and the logic device can be large, which will improve a data transfer rate, and accordingly, improve system performance.
(2) The data bus formed between the DRAM and the logic device is formed of on-chip interconnection lines, and the data bus has a capacitance smaller than the wires on the printed board. Therefore, an operation current in data transfer can be smaller, and high-speed data transfer can be achieved.
(3) A system is constituted by a single package. Accordingly, a data bus interconnection and a control signal interconnection are not needed externally, and an area occupied on the printed board can be smaller. Thus, the size of the system can be reduced.
FIG. 17 schematically shows an example of a configuration of a conventional DRAM-embedded system LSI. In FIG. 17, a DRAM-embedded system LSI 500 includes a logic 502 performing a prescribed processing, a DRAM macro 504 for storing at least data required by logic 502, and a logic external bus 508 connecting logic 502 to an external device via a pad group 518.
Logic 502 may be a dedicated logic device performing a prescribed processing, or may be a microprocessor, as far as it performs a process using the data stored in DRAM macro 504.
DRAM macro 504 includes a DRAM core 510 storing data, a test interface circuit (TIC) 512 for performing a test through external, direct access to DRAM core 510, and a selection circuit 517 for selecting either one of an internal logic bus 506 for logic 502 or an internal test bus 516 from test interface circuit 512, and connecting the selected one to an internal memory bus 515, which in turn is connected to DRAM core 510. Test interface circuit 512 is coupled to pad group 518 via an external test bus 514.
Buses 506, 508, 514, 515 and 516 each include signal lines transmitting a control signal, an address signal and data. Since there is no restrictive condition by the pin terminal, internal logic bus 506, internal memory bus 515 and internal test bus 516 can have a sufficient bus width.
Read data from DRAM core 510 is directly transferred to test interface circuit 512 and logic 502 without passing through select circuit 517. In FIG. 17, however, the transfer path of the internal read data is not shown for the sake of simplicity.
In FIG. 17, logic external bus 508 and external test bus 514 are shown both being coupled to pad group 518. External test bus 514 and logic external bus 508, however, may be configured so as to be selectively connected to common pads in accordance with a test mode instruction signal (not shown).
FIG. 18 shows, in a list, signals for DRAM core 510. In FIG. 18, DRAM core 510 receives, as operation control signals: a clock signal CLK; a clock enable signal CKE setting validity/invalidity of an internal clock signal in DRAM core 510; a row activating signal /ACT activating an internal row selecting operation; a row inactivating signal /PRE for driving a selected row to a non-select state; an auto-refresh instruction signal /REFA instructing refresh of memory cell data in DRAM core 510; a read operation instruction signal /RE instructing data read; and a write operation instructing signal /WR instructing a write data operation.
In addition, for addressing a memory cell, following signals are supplied to DRAM core 510: a row address signal RA less than 12:0 greater than  of 13 bits; a column address signal CA less than 3:0 greater than  of 4 bits; an address signal for spare row space addressing RAsp for designating a spare memory cell row; and an address signal for spare column space addressing CAsp for designating a spare column.
Address signal for spare row space addressing RAsp and address signal for spare column space addressing CAsp are used to access spare memory cells in DRAM core 510 to determine the spare memory cells to be defective/non-defective, in a test performed before fuse-programming of a defective address.
These address signals for spare space addressing RAsp and CAsp designate a spare memory cell space when they are at H level, and designate a normal memory cell space at L level.
Write data D less than 127:0 greater than  of 128 bits and spare data SD less than 1:0 greater than  of 2 bits are supplied to DRAM core 510, and read data Q less than 127:0 greater than  of 128 bits and spare data SQ less than 1:0 greater than  of 2 bits are output from the same. When a spare space is addressed, a spare memory cell for redundancy replacement is designated. The spare memory cell can directly be tested.
As shown in FIG. 18, DRAM core 510 has a larger number of input/output signals than a general-purpose DRAM of a discrete device. In this test operation as well, test interface circuit 512 generates signal/data as shown in FIG. 18 to DRAM core 510 in accordance with a signal supplied from an external tester.
If test interface circuit 512 transfers the signal/data shown in FIG. 18 to and from the external tester via pad group 518 using external test bus 514, the number of these signal/data lines will be larger than that of pins of the external tester, and a test could not performed. In addition, even if a test can be performed, the number of devices that can be measured simultaneously is reduced, and cost for the test increases, because one device to be tested requires a large number of signal lines/data lines.
Test interface circuit 512 is provided in order to reduce the number of pins required in the test, and to implement an external, direct access to DRAM core 510 to readily test the same.
FIG. 19 shows, in a list, external signals for test interface circuit 512. The signals shown in FIG. 19 are transferred between an external test apparatus and test interface circuit 512 via external test bus 514 shown in FIG. 17.
In FIG. 19, test clock signal TCLK and test clock enable signal TCKE are supplied to test interface circuit 512. Test clock signal TCLK and test clock enable signal TCKE are used in a test operation mode, instead of clock signal CLK and clock enable signal CKE supplied to DRAM core 510 in a normal operation mode.
Further, a chip select signal ICS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write operation instruction signal /WE are supplied to test interface circuit 512. A combination of logic levels, for example, at a rising edge of the test clock signal of these control signals including /CS, /RAs, /CAS and /WE, designates an operation mode of the DRAM core.
Test interface circuit 512 decodes these external control signals, and in accordance with the decoding result, selectively activates row activating signal /ACT, row inactivating signal /PRE, auto-refresh instruction signal /REFA, read operation instruction signal /RE, and write operation instruction signal /WE as shown in FIG. 18.
As an address signal, an address signal AD less than 12:0 greater than  of 13 bits and an address signal for spare space addressing ADsp are supplied to test interface circuit 512. A row address and a column address are applied via the same pads (terminals) in a time division multiplexed manner, and address signal for spare space addressing ADsp is applied for a spare row and a spare column also in a time division multiplexed manner.
As data, test write data TD less than 7:0 greater than  of 8 bits, test read data TQ less than 7:0 greater than  of 8 bits, and multi-bit test result output signal TQmbt of 1 bit are transferred between the external tester and test interface circuit 512.
Test interface circuit 512 expands bit width of test data TD less than 7:0 greater than  of 8 bits to data of 128 bits in test data writing, and supplies the resultant data to DRAM core 510 via selection circuit 517. In expanding the bit width of the test write data, test data TD less than 7:0 greater than  of 8 bits is repetitively copied to generate 128-bit data including sixteen 8-bit data of the same pattern.
In test data reading, test interface circuit 512 sequentially outputs, in a unit of 8 bits, 128-bit data read from DRAM core 510.
Multi-bit test result output signal TQmbt indicates a multi-bit test result regarding 128-bit test read data. Use of the multi-bit test result output signal TQmbt eliminates a need to individually determine 128-bit data to be defective/non-defective. Even if the data is output in a unit of 8 bits, a time for a test can be shortened by specifying defects only when the multi-bit result indicates a defect.
FIG. 20 shows a relation of an external control signal (a TIC control signal) applied to test interface circuit 512 with a control signal (a DRAM control signal) applied to DRAM core 510, in a form of a truth table.
In FIG. 20, a non-select state (DSEL) of DRAM macro 504 is set when chip select signal /CS is at H level. In this state, DRAM core 510 maintains the non-select state, irrespective of the logic levels of remaining control signals, that is, /RAS, /CAS and /WE.
When chip select signal /CS is set to L level, an operation mode to DRAM core 510 is designated.
In NOP where no operation mode is designated, control signals /RAS, /CAS and /WE are all set to H level. In such a state, control signals applied to DRAM core 510 all maintain H level, and a new operation mode to DRAM core 510 is not designated. Usually, DRAM core 510 maintains a stand-by state when an NOP command is applied.
When chip select signal /CS and row address strobe signal /RAS are both set to L level, and column address strobe signal /CAS and write operation instruction signal /WE are both set to H level, ACT instructing array activation is designated. In such a state, to DRAM core 510, row activating signal /ACT is set to an active state of L level. Remaining DRAM control signals each maintain an inactive state of H level.
Here, the logic level of the TIC control signal to test interface circuit 512 is determined at a rising edge or a falling edge of test clock signal TCLK.
When chip select signal /CS, row address strobe signal /RAS and write operation instruction signal /WE are set to L level, and column address strobe signal ICAS maintains H level, PRE instructing a precharge operation is designated. In such a state, row inactivating signal /PRE as the DRAM control signal is set to L level, and DRAM core 510 returns to a precharge state.
When chip select signal /CS, row address strobe signal /RAS and column address strobe signal /CAS are set to L level, and write operation instruction signal /WE is set to H level, REFA instructing a refresh operation is designated. In such a case, among the DRAM control signals, auto-refresh instruction signal /REFA is set to L level, and refresh is carried out in DRAM core 510.
When chip select signal /CS and column address strobe signal /CAS are both set to L level, and row address strobe signal /RAS and write operation instruction signal /WE are both set to H level, RE instructing data read is designated. In such a case, among the DRAM control signals, read operation instruction signal /RE is set to an active state of L level, and remaining DRAM control signals each maintain H level.
When chip select signal /CS, column address strobe signal /CAS, and write operation instruction signal /WE are set to L level, and row address strobe signal /RAS is set to H level, WE instructing data write is designated. In such a state, among the DRAM control signals, write operation instruction signal /WR is set to L level.
In test interface circuit 512, the TIC control signals are converted to the DRAM control signals in accordance with the truth table shown in FIG. 20. Address multiplexing, conversion of data bit width, and conversion of the control signals are performed in test interface circuit 512, thereby significantly reducing the number of pin terminals used when the external tester makes an access to DRAM core 510 for a test operation. In addition, the control signals applied to test interface circuit 512 is the same as those used for a normal, clock synchronous DRAM. Therefore, DRAM core 510 can be tested with a tester for a standard clock synchronous DRAM.
FIG. 21 schematically shows a configuration of DRAM core 510 and test interface circuit (TIC) 512 shown in FIG. 17. In FIG. 21, select circuit 517 arranged between DRAM core 510 and test interface circuit 512 is not shown for the sake of simplicity.
In FIG. 21, DRAM core 510 includes DRAM arrays 550e and 550w each having a plurality of memory cells arranged in rows and columns, and a decoder 552 selecting a memory cell from these DRAM arrays 550e and 550w in accordance with the address signal.
As an example, DRAM arrays 550e and 550w each have a storage capacity of 8 M bits.
In these DRAM arrays 550e and 550w, a spare row and a spare column for repairing a defective memory cell are provided.
Decoder 552 includes both of a row decoder for selecting a memory cell row and a column decoder for selecting a memory cell column in these DRAM arrays 550e and 550w. 
In addition, DRAM core 510 includes a DRAM data path 556e for inputting/outputting data to/from DRAM array 550e, a DRAM data path 556w for inputting/outputting data to/from DRAM array 550w, and a DRAM control circuit 558 controlling an internal operation of DRAM core 510.
DRAM data paths 556e and 556w each include a write driver transferring internal write data to corresponding DRAM arrays 550e and 550w, and a preamplifier for amplifying memory cell data read from corresponding DRAM arrays 550e and 550w. 
DRAM data path 556e transfers write data WD less than 127:64 greater than  via a write data bus 551e having a width of 64 bits, and receives internal read data RD less than 127:64 greater than  of 64 bits transferred from the DRAM array 550e via an internal read data bus 553e. 
In this DRAM array 550e, a spare column is selected simultaneously with a normal column. Therefore, in repairing a defective column, DRAM data path 556e transfers spare write data SWD less than 1 greater than  via a spare write data line 557e, and receives read data SRD less than 1 greater than  from a spare memory cell via a spare read data line 559e. 
Similarly, DRAM data path 556w transfers internal write data WD less than 63:0 greater than  to DRAM array 550w via an internal write data bus 551w having a width of 64 bits, and receives internal read data RD less than 63:0 greater than  of a width of 64 bits from DRAM array 550w via an internal read data bus 553w. 
In addition, in repairing a defective column, DRAM data path 556w receives read data SRD less than 0 greater than  read from a spare column via a spare read data line 559w, and transfers write data SWD less than 0 greater than  to a spare column via a spare write data line 557w. 
In repairing a defective column in a normal operation mode, DRAM data path 556e replaces a corresponding write data line in internal write data bus 551e with spare write data line 557e, and replaces spare read data line 559e with a corresponding internal read data line in internal read data bus 553e. Similarly, in repairing a defective column in the normal operation mode, DRAM data bus 556w replaces spare read data line 559w with a corresponding internal read data line in internal read data bus 553w, and replaces spare write data line 557w with a corresponding internal write data line in internal write data bus 551w. 
In a test mode for repair determination before programming a defective address for repairing a defective column, a normal memory cell and a spare memory cell are tested, and whether the spare memory cell functions normally is tested. In a test of a memory for repair determination, spare read data lines 559e and 559w as well as spare write data lines 557e and 557w in DRAM data paths 556e and 556w transfer data to test interface circuit 512 without replacement by a normal data line.
Test interface circuit 512 includes TIC data paths 560e and 560w provided corresponding to DRAM data paths 556e and 556w respectively, and a TIC control circuit 562 transferring test write data TD less than 7:0 greater than , test read data TQ less than 7:0 greater than , and multi-bit test result indicating signal TQmbt to and from the external tester.
TIC control circuit 562 also receives from the external tester, address signals and control signals designating an operation mode as shown in FIG. 12. In FIG. 21, however, the control signal and the addressing signal supplied to TIC control circuit 562 are not shown for the sake of simplicity.
In test data writing, TIC data paths 560e and 560w each expand test write data TD less than 7:0 greater than  of 8 bits to test data of 64 bits, and transfer the resultant data to DRAM data paths 556e and 556w via corresponding data buses 561e and 561w. 
In data reading, these TIC data paths 560e and 560w receive read data of 64 bits (read data of the total of 128 bits) from DRAM data paths 556e and 556w via data buses 563e and 563w, respectively.
TIC data path 560e receives data Q less than 127:64 greater than  of 64 bits from DRAM data path 556e via data bus 563e, and receives as spare data SQ less than 1 greater than  via spare read data line 569e, spare read data SRD less than 1 greater than  from spare internal read data line 559e transmitted via DRAM data path 556e. 
This TIC data path 560e transfers write data D less than 127:64 greater than  of 64 bits via internal write data bus 561e to DRAM data path 556e, and transfers spare write data SD less than 1 greater than  to internal spare write data line 557e via a spare write data line 567e. 
Similarly, TIC data path 560w receives internal read data Q less than 63:0 greater than  from DRAM data path 556w via read data bus 563w, and receives spare read data SQ less than 0 greater than  via spare data line 569w. In addition, this TIC data path 560w transfers data D less than 63:0 greater than  of 64 bits to DRAM data path 556w via write data bus 561w, and transfers spare write data SD less than 0 greater than  to DRAM data path 556w via a spare write data line 567w. 
In data reading, TIC control circuit 562 sequentially outputs as test data TQ less than 7:0 greater than , data of the total of 128 bits supplied to TIC data paths 560e and 560w in a unit of data of 8 bits. TIC control circuit 562 also transfers, via a multi-bit signal line 573, signal TQmbt indicating a multi-bit test result of the 128-bit data simultaneously read. When the multi-bit test result indicating signal TQmbt indicates mismatch, a defective memory cell is specified in the external tester in accordance with the test read data TQ less than 7:0 greater than  and expected value data.
FIG. 22 schematically shows a configuration of a main portion of DRAM arrays 550e and 550w. As DRAM arrays 550e and 550w have an identical configuration, FIG. 22 shows one DRAM array 550 as a representative.
In FIG. 22, DRAM array 550 includes a normal memory cell NMC arranged in rows and columns, and a spare memory cell SMC for repairing a defective normal memory cell. The spare memory cells SMC are also arranged in rows and columns, and normal memory cells NMC and spare memory cells SMC are arranged in an alignment in a direction of row. In FIG. 22, one normal memory cell NMC and one spare memory cell SMC are shown as a representative.
A word line WL is arranged in common to normal memory cells NMC and spare memory cells SMC aligned in a direction of row. A word line select signal is transmitted to word line WL from a row decoder included in decoder 552 shown in FIG. 21.
A pair of normal bit lines NBL and /NBL are arranged, corresponding to each column of normal memory cells NMC. Similarly, a pair of spare bit lines SBL and /SBL are arranged, corresponding to a column of spare memory cells SMC. In FIG. 22, only bit lines NBL and SBL are shown.
Extending to a direction of column, internal read data lines RDL0 to RDL63 and internal write data lines WDL0 to WDL63 are each arranged for a prescribed number of bit line pairs. Extending to a direction of column, spare read data line SRDL and internal spare write data line SWDL are arranged for spare memory cells SMC.
In order to select a memory cell, a write column select line WCSL transmitting a write column select signal in data writing and a read column select line RCSL transmitting a column select signal in data reading are arranged, extending in a direction of row. A write column select gate WSG arranged to a normal bit line NBL is rendered conductive by write column select line WCSL, to connect normal bit line NBL to a corresponding internal write data line WDL. In addition, in data reading, normal bit line is coupled to an internal read data line RDL via a read column select gate RSG in accordance with a signal on a read column select line RCSL. FIG. 22 shows, as a representative, read column select gate RSG and write column select gate WSG provided for internal read data line RDL0 and internal write data line WDL0.
For a spare bit line SBL as well, a spare write column select gate SWSG connecting spare bit line SBL to a spare write data line SWDL in accordance with a signal on write column select line WCSL, and a read column select gate SRSG connecting spare bit line SBL to an internal read data line SRDL in accordance with a column select signal on a read column select line RCSL are provided.
Column select lines WCSL and RCSL are arranged extending in a direction of row. Therefore, normal memory cells and a spare memory cell are always selected simultaneously, and memory cell data is read to internal read data lines RDL0 to RDL63 and spare read data line SRDL. In addition, in data writing, data are transmitted to internal write data lines WDL0 to WDL63 and spare write data line SWDL. In data writing, data is written in a defective column, as in the spare memory cell.
In decoder 552 shown in FIG. 21, a row decoder and a column decoder are arranged along the same direction so that multi-bit data interconnection lines WDL less than 127:0 greater than  and RDL less than 127:0 greater than  can be provided over a memory cell array, and an array area can be reduced. A configuration in which the row and column decoders are arranged along the same direction is commonly used in a DRAM macro merged with a logic.
FIG. 23 schematically shows an arrangement of a sense amplifier for one write data line and one read data line. In FIG. 23, a sense amplifier group SAG including sixteen sense amplifiers is arranged for internal read data line RDL and internal write data line WDL. One of sixteen sense amplifiers included in sense amplifier group SAG is selected by column address CA less than 3:0 greater than  of 4 bits. Therefore, sixteen columns of spare memory cells SMC are also provided for one spare data line. The sense amplifiers are arranged corresponding to the respective bit line pairs, and senses, amplifies and latches memory cells data of the corresponding bit line pairs when activated.
Usually, DRAM array 550 is divided into sixteen row blocks, and 512 word lines are arranged in each row block. One word line is selected in one row block by a row address RA less than 12:0 greater than  of 13 bits. In order to repair a defective memory cell row, a spare row is similarly provided. For an arrangement of the spare row, spare word lines may be provided in each row block, or may be concentrated in a specific row block.
FIG. 24 schematically illustrates a manner of repairing a defective column. One DRAM array is divided into a plurality of row blocks. FIG. 24 shows two row blocks RBi and RBj. In the DRAM array, extending in common to row blocks in a direction of column, internal read data lines RDL0 to RDL63, internal write data lines WDL0 to WDL63, spare read data line SRDL, and spare write data line SWDL are provided.
If a memory cell associated with an internal read data line RDLa and an internal write data line WDLa is defective in row block RBi, the internal read data line RDLa and internal write data line WDLa are replaced with spare read data line SRDL and spare write data line SWDL. On the other hand, if a memory cell associated with an internal read data line RDLb and an internal write data line WDLb is defective in row block RBj, internal read data line RDLb and internal write data line WDLb are replaced with spare read data line SRDL and spare write data line SWDL.
Therefore, when a row block is specified, an internal read data line or an internal write data line to be replaced is uniquely determined. Repairing of a defective memory cell is performed in units of data lines. Thus, even when column select lines, that is, the write column select lines and the read column select lines, extend in the row direction, and the spare memory cell and the normal memory cells are also simultaneously selected, a defective memory cell can be repaired through accurate redundancy replacement.
FIG. 25 schematically shows a configuration of DRAM data paths 556e and 556w shown in FIG. 21. Since DRAM data paths 556e and 556w have the same configuration, FIG. 25 shows a DRAM data path 556 as a representative.
In FIG. 25, DRAM data path 556 includes preamplifiers PA0 to PA63 provided respectively for internal read data lines RDL0 to RDL63, write drivers WV0 to WV63 arranged corresponding to internal write data lines WDL0 to WDL63 respectively, a spare preamplifier SPA arranged corresponding to spare read data line SDL, and a spare word driver SWV arranged corresponding to spare write data line SWDL.
In data reading, preamplifiers PA0 to PA63 and SPA are simultaneously activated by a not-shown control circuit (a DRAM control circuit 558). In data writing, write drivers WV0 to WV63 and SWV are also activated in parallel by a not-shown control circuit (the DRAM control circuit). When redundancy replacement is not carried out, spare write driver SWV may maintain an inactive state.
DRAM data path 556 further includes a redundancy control circuit CRC generating a select signal for redundancy replacement in accordance with a spare column check test mode instruction signal SPCC and a row block address RB, multiplexers (MUX) MX0 to MX63 provided corresponding to preamplifiers PA0 to PA63 respectively and selecting either one of output data of corresponding preamplifiers PA0 to PA63 and output data of spare preamplifier SPA in accordance with select signals RSEL0 to RSEL63 from redundancy control circuit CRC, read data latches RLH0 to RLH63 latching and transferring output data of respective multiplexers MX0 to MX63 in accordance with a not-shown clock signal, and output buffers OBF0 to OBF63 buffering the output data of respective read data latches RLH0 to RLH63 to generate read data Q0 to Q63.
Spare column check test mode instruction signal SPCC is activated in a test of the memory for repair determination performed before programming an address of a defective memory cell. In testing the memory for repair determination, whether a spare memory cell is defective/non-defective is tested. Spare addressing signals RAsp and CAsp are used in this test of the memory for repair determination.
When spare column check test mode instruction signal SPCC is inactive, redundancy control circuit CRC generates read select signals RSEL0 to RSEL63 so as to replace a defective read data line programmed for each row block, if any, with a spare read data line in accordance with row block address RB.
When spare column check test mode instruction signal SPCC is active, redundancy control circuit CRC sets all select signals RSEL0 to RSEL63 to an inactive state, and causes multiplexers MX0 to MX63 to select output data of corresponding preamplifiers PA0 to PA63, respectively.
DRAM data path 556 further includes a spare read data latch SRLH latching and transferring output data of spare preamplifier SPA in accordance with a not-shown clock signal when a test mode instruction signal TE is active, and a spare output buffer SOBF buffering output data of spare read data latch SRLH to generate spare read data SQ. An output state of spare read data latch SRLH may be set so as to set spare output buffer SOBF to an output high impedance state when spare column check test mode instruction signal SPCC is inactive. Alternatively, spare output buffer SOBF may be set to the output high impedance state when spare column check test mode instruction signal SPCC is inactive.
DRAM data path 556 further includes input buffers IBF0 to IBF63 provided corresponding to write data D0 to D63 respectively, write data latches WLH0 to WLH63 provided corresponding to input buffers IBF0 to IBF63 respectively, latching output data of corresponding input buffers IBF0 to IBF63 in accordance with a not-shown clock signal, and transferring the latched data to corresponding write drivers WV0 to WV63, a multiplexer MX70 for selecting one of the output data of input buffers IBF0 to IBF63 in accordance with select signals WSEL0 to WSEL63 from redundancy control circuit CRC, a spare input buffer SIBF buffering spare write data SD, a multiplexer MX71 selecting either output data of multiplexer MX70 or output data of spare input buffer SIBF in accordance with spare column check test mode instruction signal SPCC, and a spare write data latch SWLH latching output data of multiplexer MX71 in accordance with a not-shown clock signal and transferring the resultant data to spare write driver SWV.
When spare column check test mode instruction signal SPCC is inactive, multiplexer MX71 selects the output data of multiplexer MX70, for transference to spare write data latch SWLH. When spare column check test mode instruction signal SPCC is activated, multiplexer MX71 selects the output data of spare input buffer SIBF for transference to spare write data latch SWLH. Spare input buffer SIBF may be set to the output high impedance state when spare column check test mode instruction signal SPCC is inactive.
In DRAM data path 556, in the normal operation mode, redundancy replacement (data line replacement) for repairing a defective column is performed under the control of redundancy control circuit CRC. In other words, in data reading, multiplexers MX0 to MX63 replace the output data of a preamplifier corresponding to a defective read data line with the output data of spare preamplifier SPA in accordance with select signals RSEL0 to RSEL63 output by redundancy control circuit CRC. Meanwhile, in data writing, the write data transferred to the defective write data line is transferred to spare write data latch SWLH by multiplexers MX70 and MX71, and then transferred to spare write data line SWDL by spare write driver SWV.
In such a case, although the data is written in the defective column, there is caused no problem because a defective read data line for a defective memory cell is replaced with the spare read data line in data reading.
In addition, when redundancy replacement is not performed, multiplexer MX70 does not select data line. In such a case, even if spare word driver SWV is configured to write an invalid data into the spare memory cell, there is cased no problem. This is because redundant replacement is not carried out during the access to this row block and the invalid data written into the spare memory cell is not accessed.
In data reading in the test operation mode for repair determination before programming a defective address, redundancy control circuit CRC sets all select signals RSEL0 to RSEL63 to an inactive state, and multiplexers MX0 to MX63 select output data of corresponding preamplifiers PA0 to PA63 respectively. Moreover, in the test operation mode for repair determination, spare read data latch SRLH is activated, and the output data of spare preamplifier SPA is transferred and spare read data SQ is generated by spare data buffer SOBF.
In data writing in the test operation mode for repair determination, input data SP of spare input buffer SIBF is selected by multiplexer MX71, to be transmitted to spare write driver SRV via spare write data latch SWLH.
Therefore, in the test operation mode for repair determination, the spare read data line and the spare write data line can be accessed directly from the outside of the DRAM core.
FIG. 26 schematically shows a configuration of a portion associated with data writing of TIC data paths 556e and 556w shown in FIGS. 21. FIGS. 26 also shows a configuration of a portion generating write data of TIC control circuit 562.
TIC control circuit 562 includes a cycle shift circuit 600 transferring test data TD less than 7:0 greater than  of 8 bits in accordance with test clock signal TCLK. Cycle shift circuit 600 outputs the received test data TD less than 7:0 greater than , with a delay by a prescribed number of cycles of test clock signal TCLK.
Address signal AD less than 12:0 greater than  of 13 bits and address signal for spare address space addressing ADsp are also applied to TIC control circuit 562.
Data Df less than 7:0 greater than  of 8 bits synchronous with test clock signal TCLK is generated from cycle shift circuit 600.
TIC data path 560e includes drive circuits DRE0 to DRE7 each copying data Df less than 7:0 greater than  to generate 8-bit data, and a driver SDRe copying data Df less than 7:0 greater than  to generate spare data SD less than 1 greater than .
Drive circuits DRE0 to DRE7 each include drivers of 8 bits, and generate 8-bit data D less than 64:71 greater than , D less than 72:79 greater than , . . . and D less than 120:127 greater than , respectively. Each of these 8-bit data D less than 64:71 greater than , D less than 72:79 greater than , . . . and D less than 120:127 greater than  has the same pattern as data Df less than 7:0 greater than .
Driver SDRe is constituted with a drive circuit of 1 bit, and buffers data Df less than 7 greater than  to generate spare write data SD less than 1 greater than .
Similarly, TIC data path 560w each includes drive circuits DRW0 to DRW7 copying data Df less than 7:0 greater than  to generate data of 8 bits, and driver SDRw buffering data Df less than 7 greater than  to generate spare data SD less than 0 greater than .
Eight-bit data D less than 7:0 greater than , D less than 15:8 greater than , . . . and D less than 63:56 greater than  are generated from drive circuits DRW0 to DRW7, respectively. Eight-bit data generated from data path 560w all have the same pattern.
Here, the data pattern of test data TD less than 7:0 greater than  is expanded to 128-bit data so as to meet the following condition.
D less than 8xc2x7n+m greater than =TD less than m greater than ,
where n is an integer from 0 to 15, and m is an integer from 0 to 7.
By copying data Df less than 7:0 greater than  in TIC data paths 560e and 560w, 128-bit internal data can be generated from 8-bit external data for transmission to the DRAM core, and spare write data SD less than 0 greater than  and SD less than 1 greater than  can be transferred to the DRAM core. Spare write data SD less than 0 greater than  and SD less than 1 greater than  have the logic level similar to test data TD less than 7 greater than .
FIG. 27 schematically shows a configuration of a data read portion of TIC data paths 560e and 560w shown in FIG. 21. Since TIC data paths 560e and 560w have the same configuration, FIG. 27 shows specifically the configuration of TIC data path 560w, and that of TIC data path 560e is simply shown in a block form.
TIC data path 560w includes unit processing circuits UPW0 to UPW7 arranged corresponding to 8-bit data Q less than 7:0 greater than  to Q less than 63:56 greater than  respectively, and a tristate buffer 600e provided for spare read data SQ less than 0 greater than . These unit processing circuits UPW0 to UPW7, having the same configuration, each include a tristate buffer circuit 610 buffering corresponding 8-bit data Q to generate internal data TQf less than 7:0 greater than  when activated, and a comparison circuit 612 comparing corresponding 8-bit internal read data Q with expected value data CMPD less than 7:0 greater than  and compressing the comparison result into 1-bit data for output.
Tristate buffer circuit 610 is activated in accordance with a corresponding select signal QSEL among a 16-bit select signal QSEL less than 15:0 greater than  generated from TIC control circuit 562 in accordance with an address signal. Tristate buffer 600w is selectively activated in accordance with a select signal SQSEL less than 0 greater than  from the TIC control circuit.
TIC data path 560e includes a tristate buffer circuit 600e provided for spare data SQ less than 1 greater than , and unit processing circuits UPE0 to UPE7 provided respectively for 8-bit data Q less than 64:71 greater than  to Q less than 120:127 greater than . These unit processing circuits UPE0 to UPE7 are also selectively activated in accordance with a corresponding select signal among 16-bit select signal QSEL less than 15:0 greater than .
These unit processing circuits UPE0 to UPE7 each include a tristate buffer circuit buffering the corresponding 8-bit data to generate internal read data TQf less than 7:0 greater than  when activated, and comparison circuit 612 performing a multi-bit test of detecting match/mismatch between the respective data bits and expected value data CMPD less than 7:0 greater than .
Comparison circuit 612 compares 8-bit expected value data CMPD less than 7:0 greater than  with corresponding 8-bit data D less than 8xc2x7n+7:8xc2x7n greater than  for each bit, and further compresses the 8-bit signal of the result of bit by bit comparison into a 1-bit signal Qmbtf less than n greater than . Signal Qmbtf less than 15:0 greater than  of 16 bits indicating the comparison result from comparison circuit 612 is further compressed in TIC control circuit 562, and 1-bit multi-bit result indicating signal TQmbt is generated for transference to the external tester. In compression, it is simply determined whether or not the logic level of each bit of 16-bit signal Qmbtf less than 15:0 greater than  indicates a normal state (an AND operation is performed).
FIG. 28 schematically shows a configuration of a portion, generating a select signal shown in FIG. 27 in TIC control circuit 562. In FIG. 28, TIC control circuit 562 includes a flip-flop 620 for transferring address signals AD less than 12:0 greater than  and ADsp in synchronization with test clock signal TCLK to generate internal address signals intAD less than 12:0 greater than  and intADsp, a flip-flop 621 for further transferring internal address signals intAD less than 12:0 greater than  and intADsp from flip-flop 620 in synchronization with test clock signal TCLK to generate row address signal RA less than 12:0 greater than  and address signal for spare row addressing RAsp, a flip-flop 622 for transferring 4-bit address signal intAD less than 3:0 greater than  from flip-flop 620 in synchronization with test clock signal TCLK to generate column address signal CA less than 3:0 greater than , flip-flops 623-625 cascaded in three stages and transferring 4-bit internal address signals intAD less than 9:6 greater than  and intADsp from flip-flop 620 in synchronization with test clock signal TCLK, and a decoder 626 for decoding an output signal of flip-flop 625 to generate the select signals QSEL less than 15:0 greater than  and SQSEL less than 1:0 greater than .
The reason for arranging 3-stage flip-flops 623 to 625 in a preceding stage of decoder 626 is to delay the output signal of decoder 626 by a time period comparable to a latency in test data reading. The latency represents a time period required from a time point when a read operation instruction signal instructing data read is supplied from test interface circuit 512 to DRAM core 510 to a time point when the test data is read from DRAM core 510 and transmitted to test interface circuit 512. Here, the latency is assumed to be 2.
Flip-flops 620 to 625 output signals in synchronization with a rising edge of test clock signal TCLK, respectively.
FIG. 29 is a timing diagram representing an operation in reading test data of the DRAM macro shown in FIGS. 21 to 28. In the following, a reading operation of the test data of the DRAM macro will be described with reference to FIG. 29.
Test interface circuit (TIC) 512 transfers external control signals to DRAM core 510, with a delay by 1 clock cycle of test clock signal TCLK. Therefore, in DRAM core 510, the control signal and the address signal are taken in at the rising edge of test clock signal TCLK after two clock cycles since the control signal and others are supplied from the tester to test interface circuit 512, and an internal operation is carried out. Here, in FIG. 29, clock signal CLK and test clock signal TCLK supplied to DRAM core 510 are assumed to have the same waveforms.
At time T1, a control signal ACT instructing row activation is supplied, and 13-bit row address signal RA(k) is supplied concurrently. Test interface circuit (TIC) 512 decodes the externally applied control signal, and transfers the row activating signal ACT to DRAM core 510 in accordance with the decode result, in synchronization with the rising edge of clock signal TCLK. As shown in FIGS. 18 and 20, although the control signal applied to the DRAM core is a signal of a negative logic, in FIG. 29, mnemonics shown in FIG. 20 are used to represent an operation mode instruction signal.
Here, as shown in FIG. 28, row address signal RA(k) is transferred from flip-flop 621 in synchronization with the rising edge of test clock signal TCLK.
At time T3, row activating signal ACT is taken in DRAM core 510 along with row address signal RA(k) in synchronization with the rising edge of clock signal CLK, and a row select operation is internally executed.
At time T2, a write operation instruction signal instructing data write is provided to test interface circuit (TIC) 512 along with column address signal CA(m) and test data TD(m), and control signal, column address signal and test data are taken in test interface circuit (TIC) 512 in synchronization with the rising edge of test clock signal TCLK.
The control signals are decoded within test interface circuit (TIC) 512, and write operation instruction signal WRITE for DRAM core 510, column address signal CA(m), and test data TD(m) are transferred to DRAM core 510 in synchronization with the rising edge of clock signal TCLK at time T3.
Write operation instruction signal WRITE, column address signal CA(m), and data D(m) are taken in DRAM core 510 in synchronization with the rising edge of clock signal CLK at time T4, to execute a column select operation, and data D(m) of 128 bits is written in columns designated by column address CA(m).
At time T3, a command (READ) instructing data read is supplied to test interface circuit (TIC) 512 along with column address signal CA(n) and test data TD(n). Test data TD(n) in data reading is used as expected value data CMPD less than 7:0 greater than  for comparison in the data path in test interface circuit 512.
Test data TD(n) supplied to test interface circuit (TIC) 512 at T3 is not transferred to the DRAM core because the write operation is not executed in the TIC data path. In particular, at a timing shown in FIG. 29, the comparison data (expected value data) is generated by internally shifting data supplied from the external tester by a prescribed number of cycles, considering a column latency in data reading, and is supplied to comparison circuit 612 provided in test interface circuit (TIC) 512. Therefore, in the input of the comparison data, write data written in response to the write command is transferred within test interface circuit (TIC) 512 to the DRAM core. Thus, even if the write data is supplied to test interface circuit (TIC) 512 along with the read command, there is caused no problem.
On the other hand, if comparison data CMPD less than 7:0 greater than  is required to be input in a cycle before read command application due to restriction of the number of delay stages in internal generation of comparison data, there will be a restriction that the write operation is not allowed in the input cycle for comparison data.
The command (READ) supplied to test interface circuit (TIC) 512 at time T3 is decoded in test interface circuit 512, and a read operation instruction signal READ is generated. In synchronization with the rising edge of test clock signal TCLK at time T4, read operation instruction signal READ (/RE) and column address signal CA(n) are supplied to DRAM core 510. Here, the command is used in the mnemonics previously shown in FIG. 20 as an instruction for an operation mode given by a combination of a plurality of control signals.
In DRAM core 510, in synchronization with the rising edge of clock signal CLK at time T5, column select operation is carried out in accordance with read operation instruction signal READ and column address signal CA(n), and the test data is internally read.
At time T4, control signals (PRE) instructing a precharge operation are supplied to test interface circuit (TIC) 512, the control signal are decoded in test interface circuit 512, and a row inactivation instruction signal PRE is transferred to DRAM core 510. At time T6, row inactivation instruction signal PRE is taken in DRAM core 510, and the internal precharge operation is performed.
In DRAM core 510, data internally read in response to read operation instruction signal READ supplied at time T5, with a column latency of 2 cycles, is read out externally in a clock cycle starting from time T6. At time T7, read data Q(n) is supplied to test interface circuit (TIC) 512.
In test interface circuit 512, in the clock cycle starting from time T6, buffer circuit 610 is selectively activated in accordance with a select signal from decoder 626 shown in FIG. 28 to generate 8-bit data from 128-bit data Q(n) transferred from DRAM core 510. In addition, in comparison circuit 612, data TD(n) taken in at time T3 is compared with the read data, and a signal indicating the comparison result is generated by time T7.
In a clock cycle starting from time T7, test interface circuit (TIC) circuit 512 outputs 8-bit test data TQ(n) along with multi-bit test result indicating signal Qmbt(n). Decoder 626 and flip-flops 620-625 shown in FIG. 28 constantly operate in synchronization with test clock signal TCLK. Therefore, when address signals intAD less than 9:6 greater than  and ADsp shown in FIG. 28 are sequentially supplied in each clock cycle, 8-bit data is sequentially selected in accordance with select signals QSEL less than 15:0 greater than  and SQSEL less than 1:0 greater than  output by decoder 626, and the selected data is read out from test interface circuit 512.
Decoder 626 may include an address counter, which internally performs count operation in synchronization with test clock signal TCLK to generate a column address, and may decode the column address to generate select signals QSEL less than 15:0 greater than .
In the external tester, when multi-bit test result indicating signal Qmbt(n) indicates mismatch with respect to 8-bit test data TQ(n), test expected value data TD(n) is compared with test read data TQ(n) for each bit, and a position of a defective memory cell is specified. Multi-bit result indicating signal TQmbt indicates match/mismatch of the 128-bit data simultaneously selected. When multi-bit test result indicating signal TQmbt(n) indicates match, each bit of 128-bit test data TQ(n) is determined all being normal. The time for the test is shortened because it is not necessary to specify a position of a defective memory cell for each 8-bit test data with respect to all 8-bit data in the external tester.
DRAM macro 504 is integrated on the same semiconductor chip as logic 502 demanding a variety of specifications. Therefore, DRAM core 510 is required to cover the variety of specifications of logic (user logic) 502. The specifications required by the user logic are different in memory storage capacity, the number of banks, page size, the number of I/Os (input/output data bits), and others. Among the above, for the number of input/output data bits (the number of I/Os or a word configuration), for example, data paths 556w and 550e of DRAM core 510 are configured to enable switching of the number of input/output data bits with a metal slicing process.
FIG. 30 schematically shows a configuration of an IO switching portion of data paths 556w and 556e of the DRAM core with the word configuration variable. Data paths 556w and 556e have the same configuration for switching the word configuration, and the switching portion of data path 556 is representatively shown. In FIG. 30, DRAM data path 556 includes preamplifiers/write drivers PW0 to PW127 generating internal write/read data, and DQ buffers BF0 to BF127 coupled to memory data bus 515.
Each of preamplifiers/write drivers PW0 to PW127 includes preamplifier PA and write driver WV shown in FIG. 25. In data writing, a preamplifier/write driver PWi generates write data WD less than i greater than , and in data reading, amplifies internal read data RD less than i greater than  read from a selected memory cell, to generate internal read data.
DQ buffers BF0 to BF127 each include output buffers OBF and input buffers IBF shown in FIG. 25. In data writing, a DQ buffer BFi generates internal write data when receiving write data D less than i greater than , and in data reading, generates output data Q less than i greater than .
I/O switches IOS0 to IOS31 for switching the number of data input/output bits are provided between these preamplifiers/write drivers PW0 to PW127 and DQ buffers BF0 to BF127. Each of these I/O switches IOS0 to IOS31 is arranged corresponding to four adjacent internal data input/output lines I/Os. The number of input/output data bits is switched by switching the internal connection paths in each of I/O switches IOS0 to IOS31.
In a configuration of the data path shown in FIG. 30, the maximum number of data input/output bits is 128 bits. Three types of word configurations, that is, input/output of 128-bit data, input/output of 64-bit data, and input/output of 32-bit data, are implemented by switching the connection paths in a similar manner in I/O switches IOS0 to IOS31.
In an arrangement shown in FIG. 30, I/O switches IOS0 to IOS31 are arranged between multiplexers MUX0 to MUX63 for redundancy replacement shown in FIG. 25 and read data latches RLH0 to RLH63, as well as between internal write data latches WLH0 to WLH63 and write drivers WV0 to WV63. In FIG. 30, however, these multiplexers for repairing a defect and latch circuits for internal data transfer are not shown for the sake of simplicity.
An I/O switch IOS is arranged for adjacent internal data lines I/O, and in each of I/O switches IOS0 to IOS31, connection of a preamplifier/write driver PW to a DQ buffer DF is switched. Thus, the word configuration is switched between 128-bit data, 64-bit data and 32-bit data.
Here, the internal data line I/O includes an internal write data line IL and an internal read data line OL. The internal data lines are arranged into a separated IO configuration, and write data and read data are transferred via separately provided data lines.
FIG. 31 shows more specifically a configuration of I/O switches IOS0 to IOS31 shown in FIG. 30. In FIG. 31, as these I/O switches IOS0 to IOS31 have the same configuration, one IO switch IOSn is shown as a representative.
I/O switch IOSn is arranged between DQ buffers BF4n to BF4n+3 and preamplifiers/write drivers PW4n to PW4n+3. A multiplexer for redundancy replacement is arranged between I/O switch IOSn and preamplifiers/write drivers PW4n to PW4n+3 (with regard to a read path).
Preamplifier/write driver PW4n includes a write driver WV4n and a preamplifier PA4n. Write drivers WV4n+1 to WV4n+3 and preamplifiers PA4n+1 to PA4n+3 are arranged also in other preamplifiers/write drivers PW4n+1 to PW4n+3.
DQ buffers BF4n to BF4n+3 include input buffers IBF4n to IBF4n+3 and output buffers OBF4n to OBF4n+3 respectively.
I/O switch IOSn includes metal switches MSWW0 and MSWR0 arranged for a preamplifier/write driver PW4n+1, metal switches MSWW1 and MSWR1 provided for a preamplifier/write driver PW4n+3, a switch gate ESWW0 rendered conductive when a test mode instruction signal ZMTEST is activated and connecting metal switch MSWW0 to an internal write data line IL41, a switch gate ESWR0 rendered conductive when test mode instruction signal ZMTEST is activated and connecting metal switch MSWR0 to an internal read data line OL4n+1, a switch gate ESWW1 rendered conductive when test mode instruction signal ZMTEST is activated and coupling metal switch MSWW1 to a metal switch MSWW2, a switch gate ESWR2 rendered conductive when test mode instruction signal ZMTEST is activated and connecting an internal read data line OL4n+2 to a metal switch gate MSWR2, a switch gate ESWW2 rendered conductive when test mode instruction signal ZMTEST is activated and connecting an internal write data line IL4n+1 to metal switch MSWR2, and a switch gate ESWR1 rendered conductive when test mode instruction signal ZMTEST is activated and coupling metal switch MSWR1 to an internal read data line OL4n+3 when conductive.
Test mode instruction signal ZMTEST is an inverted signal of a test mode instruction signal MTEST supplied to select circuit 517 shown in FIG. 17, and is set to L level (an active state) in the test operation mode.
Metal switch MSWW2 couples switch gates ESWW2 and ESWW1 to an internal write data line IL4n when conductive. Metal switch MSWR0 couples switch gate ESWR2 and metal switch MSWR1 to an internal read data line OL4n when conductive.
DQ buffers BF4n to BF4n+3 are set to enable/disable state respectively by 4-bit DQ select signal DQSEL less than 3:0 greater than  having respective logic levels set by a metal interconnection.
On the other hand, preamplifiers/write drivers PW4n to PW4n+3 are selectively activated in accordance with DQ select signal DQSEL less than 3:0 greater than  and 4-bit IO select signal IOSEL less than 3:0 greater than  generated based on not-shown column address signal CA less than 5:4 greater than .
Respective connection paths of metal switches MSWW0 to MSWW2 and MSWR0 to MSWR2 are set through the metal interconnection in a slice process. Switch gates ESWW0 to ESWW2 and ESWR0 to ESWR2 are rendered non-conductive when test mode instruction signal ZMTEST is activated in the test mode. In the normal operation mode, test mode instruction signal ZMTEST is inactive, and these switch gates ESWW0 to ESWW2 and ESWR0 to ESWR2 maintain a conductive state.
Therefore, in the test operation mode, preamplifiers/write drivers PW4n to PW4n+3 are coupled to corresponding DQ buffers BF4n to BF4n+3 respectively, irrespective of the connection path of a metal switch MSW (collectively representing metal switches). In the normal operation mode, the data line is connected in accordance with the connection path of metal switch MSW.
FIG. 32 schematically shows a connection state of I/O switch IOSn in a 128 I/O mode (a full I/O mode). In the 128 I/O mode, metal switches MSWW0 to MSWW2 and MSWR0 to MSWR2 are all set to a non-conductive state. In that state, preamplifiers/write drivers PW4n to PW4n+3 are coupled to corresponding DQ buffers BF4n to BF4n+3 via internal data lines IOL4n to IOL4n+3.
In the full I/O mode, DQ buffers BF4n to BF4n+3 are all set to an operable state in accordance with DQ select signals DQSEL less than 3:0 greater than , and IO select signals IOSEL less than 3:0 greater than  are also all set to a selected state. Therefore, as all preamplifiers/write drivers PW4n to PW4n+3 operate, and DQ buffers BF4n to BF4n+3 also operate, 4-bit data is transferred via I/O switch IOSn. Therefore, a total of 128-bit data is transferred by I/O switches IOS0 to IOS31.
FIG. 33 schematically shows a connection of the internal data line in a 64 I/O mode (a half I/O mode). In the 64 I/O mode, metal switches MSWW2 and MSWR2 are set to a non-conductive state, and remaining metal switches MSWW0, MSWW1, MSWR0 and MSWR2 are set to a conductive state. In that state, internal data line IOL4n+1 is coupled to internal data line IOL4n, and internal data line IOL4n+3 is coupled to internal data line IOL4n+2.
DQ buffers BF4n+1 and BF4n+3 are set to a non-operable state by DQ select signals DQSEL less than 3:0 greater than . A set of preamplifiers/write drivers PW4n and PW4n+2 or PW4n+1 and PW4n+3 is activated in accordance with IO select signals IOSEL less than 3:0 greater than . Therefore, since 2-bit data is transferred in one I/O switch IOSn, a total of 64-bit data transfer is performed.
FIG. 34 schematically shows a connection path of I/O switch IOSn in a 32 I/O mode (a quarter I/O mode). In the 32 I/O mode, metal switches MSWW0 to MSWW2 and MSWR0 to MSWR2 are all set to a conductive state. Therefore, preamplifiers/write drivers PW4n+1 to PW4n+3 are all coupled to internal data line IOL4n. 
DQ buffers BF4n+1 to BF4n+3 are set to a non-operable state in accordance with DQ select signals DQSEL less than 3:0 greater than , and DQ buffer BF4n is set to an operable state. In addition, one of preamplifiers/write drivers PW4n to PW4n+3 is activated in accordance with IO select signals IOSEL less than 3:0 greater than . Therefore, in I/O switch IOSn, 1-bit data is transferred, and a total of 32-bit data transfer is performed.
In the test operation mode, switch gates ESWW0 to ESWW2 and ESWR0 to ESWR2 are all set to a non-conductive state in accordance with test mode instruction signal ZMTEST. Therefore, a state in which these metal switches MSWW0 to MSWW2 and MSWR0 to MSWR2 are set to a non-conductive state is equivalently implemented, irrespective of conductive/non-conductive states of metal switches MSWW0 to MSWW2 and MSWR0 to MSWR2. Internal data lines IOL4n to IOL4n+3 are isolated from each other.
In addition, IO select signals IOL less than 3:0 greater than  and DQ select signals DQSEL less than 3:0 greater than  are all activated in the data write/read operation in the test mode of operation. Therefore, in the test mode, the full I/O mode is implemented irrespective of its practical word configuration, and accordingly, 128-bit data transfer is carried out between the DRAM core and the test interface circuit (TIC). Thus, the time for the test is shortened by performing 128-bit data transfer in the test operation mode even for the DRAM core having a smaller number of input/output data bits (the number of I/Os).
When a DRAM core with a data path the number of input/output data bits (the number of I/Os) made varied in a metal slice process is tested solely, all data bit transfer paths are activated in accordance with test mode instruction signal ZMTEST.
Normally, an operation margin of the DRAM core is tested via the aforementioned test interface circuit (TIC), not via the user logic (logic). This is because, when the DRAM core is tested via the user logic (logic), access patterns for the DRAM core are restricted, and sufficient screening is not achieved. For example, when the logic (user logic) is constituted with a processor with a primary cache embedded, the DRAM core is not accessed if the primary cache is hit. Therefore, access load cannot continuously be applied to the DRAM core.
When the single DRAM core is tested solely via the test interface circuit, the test is simply performed with the data path set to the maximum data bit number of the DRAM core. Therefore, when the single DRAM core with a word configuration variable is tested, the test is carried out under the configuration different from the configuration in the actual use. Accordingly, whether the I/O switch is operating normally or not cannot be tested. In addition, because the configuration of the data path is different from that in the actual use, it is not possible to accurately test whether or not the DRAM core has a sufficient operation margin, even when the operation margin is tested.
Therefore, when shipped in a wafer state and the whole of a product including the logic is tested at a delivered side or a user, an I/O switch failure or an operation margin failure may occur, to lower the yield.
Moreover, when the DRAM core is tested via the user logic (logic) in order to ensure such an operation margin, sufficient screening cannot be performed due to the restriction of the test patterns and others. Therefore, if a final product incorporates this system LSI, system malfunction might be caused, to lower the yield of the final product.
If the yield is decreased, the cost for the product will be higher, and the cost/performance will be lower.
In addition, the word configuration of the DRAM core, even if it can be varied, is set in a fixed manner through the metal interconnection in the slice process. Therefore, when a system including logics having different word configurations is constructed, the DRAM core should be arranged for each logic, and the word configuration thereof should be adapted to the corresponding logic. According to such a system configuration, a plurality of DRAM cores are necessary in accordance with the word configurations, and the system LSI should be constructed for each logic. It is therefore, difficult to integrate logics having different word configurations on one system LSI, and the system size will increase. Further, in order to share data among logics, it is necessary to arrange a common buffer memory outside the system LSI, which will increase the system size.
An object of the present invention is to provide a semiconductor integrated circuit device capable of effecting sufficient screening on a single DRAM core solely.
Another object of the present invention is to provide a semiconductor integrated circuit device capable of testing a single DRAM core having a word configuration variable under the same condition as in an actual use.
Yet another object of the present invention is to provide a semiconductor integrated circuit device having a DRAM core, of which word configuration can be easily varied in an actual use.
A semiconductor integrated circuit device according to the present invention includes a plurality of internal data lines; a plurality of internal write/read circuits arranged corresponding to the plurality of internal data lines, and each activated in response to a select signal to communicate data with a corresponding internal data line when activated; and a plurality of data input/output circuits arranged corresponding to the plurality of internal write/read circuits, each selectively made operable in accordance with data bit number designating information, activated in response to a data access instruction signal when made operable, and communicating data with a corresponding internal write/read circuit when activated. The data bit number designating information can externally be varied.
The semiconductor integrated circuit device according to the present invention further includes a connection circuit connecting the plurality of internal write/read circuits to the plurality of data input/output circuits, and a path setting circuit setting a connection path in the connection circuit in accordance with the data bit number designating information. The connection circuit includes a switching circuit for electrically setting a connection path between the internal read/write circuit and the data input/output circuit in accordance with the data bit number designating information.
The connection path setting the connection path between the internal write/read circuit and the data input/output circuit can electrically be varied. Thus, the data path can be operated under an actual use condition in a test, and a function of an I/O switch and an operation margin can be tested.
In addition, by testing the single DRAM core solely via the test interface circuit, the DRAM core can directly be tested from the outside using a variety of test patterns, and accurate screening can be carried out. Thus, the yield is improved.
Further, data for setting the connection path can be made accessible from the logic by arranging a circuit for storing the data within the DRAM core. Accordingly, in one system LSI, when a plurality of processors make an access to the DRAM core, each processor can individually set a word configuration for the access, even-if each processor has a different word configuration. Thus, the system will be readily configured, and the system size can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.